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gal22lv10z gal22lv10zd low voltage, zero power e 2 cmos pld 1 description the gal22lv10z and gal22lv10zd, at 15ns maximum propa- gation delay time and 100 a standby current, combine 3.3v cmos process technology with electrically erasable (e 2 ) floating gate tech- nology to provide the best pld solution to support today's new 3.3v systems. e 2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. the generic 22v10 architecture provides maximum design flexibility by allowing the output logic macrocell (olmc) to be configured by the user. the gal22lv10z uses input transition detection (itd) to put the device into standby mode and is fully function/fuse map/ parametric compatible with standard bipolar and cmos 22v10 de- vices. the gal22lv10zd utilizes a dedicated power-down pin (dpp) to put the device into standby mode. unique test circuitry and reprogrammable cells allow complete ac, dc, and functional testing during manufacture. as a result, lat- tice semiconductor is able to deliver 100% field programmability and functionality of all gal products. in addition,100 erase/re- write cycles and data retention in excess of 20 years are specified. 228 nc i/clk i i i/dpp i i i i i nc nc nc gnd i i i i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q vcc i/o/q i/o/q i/o/q 42 6 25 19 18 21 23 16 14 12 11 9 7 5 programmable and-array (132x44) i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q *gal22lv10zd only i i/clk i i i/dpp* i i i i i i i reset preset 8 10 12 14 16 16 14 12 10 8 olmc olmc olmc olmc olmc olmc olmc olmc olmc olmc plcc copyright ? 1997 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. july 1997 tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com gal22lv10z gal22lv10zd top view 22lv10zd_02 features 3.3v low voltage, zero power operation interfaces with standard 5v ttl devices ?0 a typical standby current (100 a max.) 40ma typical active current (55ma max.) input transition detection on gal22lv10z dedicated power-down pin on gal22lv10zd high performance e 2 cmos technology 15 ns maximum propagation delay fmax = 71.4mhz ultramos advanced cmos technology compatible with standard 22v10 devices fully function/fuse-map/parametric compatible with bipolar and cmos 22v10 devices ? 2 cell technology reconfigurable logic reprogrammable cells 100% tested/100% yields high speed electrical erasure (<100ms) 20 year data retention ten output logic macrocells maximum flexibility for complex logic designs preload and power-on reset of registers 100% functional testability applications include: battery powered systems dma control state machine control electronic signature for identification functional block diagram pin configuration discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications gal22lv10z gal22lv10zd 2 )sn(dpt us t1 ) sn( )sn(oc t) am(cc i( bsi ) a# gniredr oe gakcap 5 10 10 15 50 0 1j q51-z01vl22la gc clpdael-82 5 25 15 15 50 0 1j q52-z01vl22la gc clpdael-82 gal22lv10zd: commercial grade specifications )sn(dpt us t1 ) sn( )sn(oc t) am(cc i( bsi ) a# gniredr oe gakcap 5 10 10 15 50 0 1j q51-dz01vl22la gc clpdael-82 5 25 15 15 50 0 1j q52-dz01vl22la gc clpdael-82 blank = commercial grade package active power q = quarter power xxxxxxxx xx x x x device name _ j = plcc gal22lv10z (zero power itd) gal22lv10zd (zero power dpp) speed (ns) gal22lv10z and gal22lv10zd ordering information gal22lv10z: commercial grade specifications part number description discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications gal22lv10z gal22lv10zd 3 gal22lv10z and gal22lv10zd output logic macrocell (olmc) each of the macrocells of the gal22lv10z and gal22lv10zd have two primary functional i/o modes: registered, and combina- torial. the modes and the output polarity are set by two bits (so and s1), which are normally controlled by the logic compiler. each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. registered in registered mode the output pin associated with an individual olmc is driven by the q output of that olmc s d-type flip-flop. logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). output tri-state control is available as an in- dividual product-term for each olmc, and can therefore be defined by a logic equation. the d flip-flop s q output is fed back into the and array, with both the true and complement of the feedback available as inputs to the and array. note: in registered mode, the feedback is from the q output of the register, and not from the pin; therefore, a pin defined as reg- istered is an output only, and cannot be used for dynamic i/o, as can the combinatorial pins. combinatorial i/o in combinatorial mode the pin associated with an individual olmc is driven by the output of the sum term gate. logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as ei- ther on (dedicated output), off (dedicated input), or product-term driven (dynamic i/o). feedback into the and array is from the pin side of the output enable buffer. both polarities (true and inverted) of the pin are fed back into the and array. the gal22lv10z and gal22lv10zd have a variable number of product terms per olmc. of the ten available olmcs, two olmcs have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two olmcs have sixteen product terms (pins 21 and 23). in addition to the product terms available for logic, each olmc has an addi- tional product-term dedicated to output enable control. the output polarity of each olmc can be individually programmed to be true or inverting, in either combinatorial or registered mode. this allows each output to be individually configured as either active high or active low. the gal22lv10z and gal22lv10zd have a product term for asynchronous reset (ar) and a product term for synchronous pre- set (sp). these two product terms are common to all registered olmcs. the asynchronous reset sets all registers to zero any time this dedicated product term is asserted. the synchronous preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. note: the ar and sp product terms will force the q output of the flip-flop into the same state regardless of the polarity of the output. therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. ar sp d q q clk 4 to 1 mux 2 to 1 mux output logic macrocell (olmc) output logic macrocell configurations discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications gal22lv10z gal22lv10zd 4 active high active low active high active low s 0 = 1 s 1 = 1 s 0 = 0 s 1 = 1 s 0 = 0 s 1 = 0 s 0 = 1 s 1 = 0 ar sp d q q clk ar sp d q q clk registered mode combinatorial mode discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications gal22lv10z gal22lv10zd 5 * note: input not available on gal22lv10zd plcc package * 2 26 olmc s0 5810 s1 5811 0440 . . . . 0880 3 asynchronous reset (to all registers) 0 4 8 1216202428323640 synchronous preset (to all registers) 12 0000 5764 0044 . . . 0396 27 s0 5808 s1 5809 25 olmc s0 5812 s1 5813 0924 . . . . . 1452 4 5 6 24 olmc s0 5814 s1 5815 1496 . . . . . . 2112 23 olmc s0 5816 s1 5817 2156 . . . . . . . 2860 21 olmc s0 5818 s1 5819 2904 . . . . . . . 3608 20 olmc s0 5820 s1 5821 3652 . . . . . . 4268 olmc s0 5822 s1 5823 4312 . . . . . 4840 10 19 18 olmc s0 5824 s1 5825 4884 . . . . 5324 11 5368 . . . 5720 17 olmc s0 5826 s1 5827 9 7 13 16 8 10 14 16 12 12 16 14 10 8 olmc electronic signature 5828, 5829 ... ... 5890, 5891 l s b m s b byte 7 byte 6 byte 5 byte 4 byte 2 byte 1 byte 0 byte 3 gal22lv10z and gal22lv10zd logic diagram/jedec fuse map discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications gal22lv10z gal22lv10zd 6 recommended operating conditions commercial devices: ambient temperature (t a ) ............................. 0 to +75 c supply voltage (v cc ) with respect to ground ......................... +3.0 to +3.6v v il input low voltage vss 0.5 0.8 v v ih input high voltage 2.0 5.25 v i il input or i/o low leakage current 0v v in v il (max.) - 10 a i ih input or i/o high leakage current (v cc ? 0.2)v v in v cc 10 a v cc v in 5.25 v 1ma v ol output low voltage i ol = max. vin = v il or v ih 0.5 v i ol = 0.5 ma v in = v il or v ih 0.2 v v oh output high voltage i oh = max. v in = v il or v ih 2.4 v i oh = -0.5 ma v in = v il or v ih vcc-0.45 v i oh = -100 a v in = v il or v ih vcc-0.2 v i ol low level output current 8ma i oh high level output current -8 ma i os 1 output short circuit current v cc = 3.3v v out = 0.5v t a = 25 c -30 -130 ma symbol parameter condition min. typ. 2 max. units commercial i sb stand-by power v il = gnd v ih = vcc outputs open z -15/-25 50 100 a supply current zd -15/-25 i cc operating power v il = gnd v ih = 3.0v z -15/-25 40 55 ma supply current f toggle = 5 mhz outputs open zd -15/-25 1) one output at a time for a maximum duration of one second. vout = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2) typical values are at vcc = 3.3v and t a = 25 c absolute maximum ratings (1) supply voltage v cc .................................... - 0.5 to +5.6v input voltage applied ................................. -0.5 to +5.6v off-state output voltage applied ................ -0.5 to +5.6v storage temperature ................................. -65 to 150 c ambient temperature with power applied ......................................... -55 to 125 c 1. stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. these are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). dc electrical characteristics over recommended operating conditions (unless otherwise specified) discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications gal22lv10z gal22lv10zd 7 specifications gal22lv10z t pd a input or i/o to combinatorial output 3 15 3 25 ns t co a clock to output delay 2 10 2 15 ns t cf 2 clock to feedback delay 10 10 ns t su1 setup time, input or fdbk before clk 10 15 ns t su2 setup time, sp before clk 14 20 ns t h hold time, input or fdbk after clk 0 0 ns a maximum clock frequency with 50 33.3 mhz external feedback, 1/(tsu + tco) f max 3 a maximum clock frequency with 50 40 mhz internal feedback, 1/(tsu + tcf) a maximum clock frequency with 71.4 50 mhz no feedback t wh clock pulse duration, high 6 10 ns t wl clock pulse duration, low 6 10 ns t en b input or i/o to output enabled 3 15 3 25 ns t dis c input or i/o to output disabled 3 15 3 25 ns t ar a input or i/o to asynch. reset of reg. 3 20 3 25 ns t arw asynch. reset pulse duration 15 25 ns t arr asynch. reset to clk recovery time 10 25 ns t spr synch. preset to clk recovery time 10 15 ns t as a last active input to standby 100 250 100 250 ns t sa 4 a standby to active output 15 20 ns -25 min. max. -15 min. max. units param test cond. 1 description com com 1) refer to switching test conditions section. 2) calculated from fmax with internal feedback. refer to fmax description section. 3) refer to fmax description section. 4) add t sa to t pd, t su, t ar, t en and t dis when the device is transitioning from standby state to active state. ac switching characteristics over recommended operating conditions power input or i/o feedback clk output t as t pd, t en, t dis icc isb t sa t su t co standby power timing waveforms discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications gal22lv10z gal22lv10zd 8 specifications gal22lv10zd t pd a input or i/o to combinatorial output 3 15 3 25 ns t co a clock to output delay 2 10 2 15 ns t cf 2 clock to feedback delay 10 10 ns t su1 setup time, input or fdbk before clk 10 15 ns t su2 setup time, sp before clk 14 20 ns t h hold time, input or fdbk after clk 0 0 ns a maximum clock frequency with 50 33.3 mhz external feedback, 1/(tsu + tco) f max 3 a maximum clock frequency with 50 40 mhz internal feedback, 1/(tsu + tcf) a maximum clock frequency with 71.4 50 mhz no feedback t wh clock pulse duration, high 6 10 ns t wl clock pulse duration, low 6 10 ns t en b input or i/o to output enabled 3 15 3 25 ns t dis c input or i/o to output disabled 3 15 3 25 ns t ar a input or i/o to asynch. reset of reg. 3 20 3 25 ns t arw asynch. reset pulse duration 15 25 ns t arr asynch. reset to clk recovery time 10 25 ns t spr synch. preset to clk recovery time 10 15 ns -25 min. max. -15 min. max. units param test cond. 1 description com com 1) refer to switching test conditions section. 2) calculated from fmax with internal feedback. refer to fmax description section. 3) refer to fmax description section. ac switching characteristics over recommended operating conditions discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications gal22lv10z gal22lv10zd 9 specifications gal22lv10zd t whd dpp pulse duration high 40 40 ns t wld dpp pulse duration low 30 40 ns t ivdh valid input before dpp high 0 0 ns t cvdh valid clock before dpp high 0 0 ns t dhix input don't care after dpp high 15 25 ns t dhcx clock don't care after dpp high 15 25 ns t ixdl input don't care before dpp low 0 0ns t cxdl clock don't care before dpp low 0 0ns t dliv dpp low to valid input or i/o 20 25 ns t dlcv dpp low to valid clock 30 35 ns t dlov a dpp low to valid output 5 35 5 45 ns parameter units -25 min. max. test cond 1 . description -15 min. max. active to standby com com standby to active 1) refer to switching test conditions section. t dhcx dpp input or i/o feedback clk output t cvdh t ivdh t dhix t pd, t en, t dis t co t dliv t dlcv t dlov t ixdl t cxdl dedicated power-down pin (dpp) specifications over recommended operating conditions dedicated power-down pin timing waveforms discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications gal22lv10z gal22lv10zd 10 valid input input or i/o feedback t pd combinatorial output input or i/o feedback registered output clk valid input t su t co t h (external fdbk) 1/ f max input or i/o to output enable/disable t en t dis input or i/o feedback output clk (w/o fdbk) t wh t wl 1/ f max registered output clk t arw t ar t arr input or i/o feedback driving ar f max with feedback clk registered feedback t cf t su 1/ f max (internal fdbk) synchronous preset symbol parameter typical units test conditions c i input capacitance 8 pf v cc = 3.3v, v i = 0v c i/o i/o capacitance 8 pf v cc = 3.3v, v i/o = 0v registered output clk input or i/o feedback driving sp t su t h t co t spr asynchronous reset clock width registered output combinatorial output switching waveforms capacitance (t a = 25 c, f = 1.0 mhz) discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications gal22lv10z gal22lv10zd 11 register logic array t co t su clk note: f max with external feedback is cal- culated from measured tsu and tco. f max with external feedback 1/( t su+ t co) register logic array clk t su + t h f max with no feedback note: f max with no feedback may be less than 1/( t wh + t wl). this is to allow for a clock duty cycle of other than 50%. input pulse levels gnd to 3.0v input rise and fall times 2ns 10% 90% input timing reference levels 1.5v output timing reference levels 1.5v output load see figure all 3-state levels are measured at (voh - 0.5) v and (vol + 0.5) v. output load conditions (see figure) test condition r 1 r 2 c l a 270 ? 220 ? 35pf b active high 270 ? 220 ? 35pf active low 270 ? 220 ? 35pf c active high 270 ? 220 ? 5pf active low 270 ? 220 ? 5pf test point c * l from output (o/q) under test +3.3v *c l includes test fixture and probe capacitance r 2 r 1 f max with internal feedback 1/( t su+ t cf) note: t cf is a calculated value, derived by sub- tracting tsu from the period of fmax w/internal feedback ( t cf = 1/ f max - t su). the value of t cf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. for example, the timing from clock to a combi- natorial output is equal to tcf + tpd. clk register logic array t cf t pd f max descriptions switching test conditions discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications gal22lv10z gal22lv10zd 12 electronic signature an electronic signature (es) is provided in every gal22lv10z and gal22lv10zd device. it contains 64 bits of reprogrammable memory that can contain user-defined data. some uses include user id codes, revision numbers, or inventory control. the signature data is always available to the user independent of the state of the security cell. the electronic signature is an additional feature not present in other manufacturers 22v10 devices. to use the extra feature of the user- programmable electronic signature it is necessary to choose a lattice semiconductor 22lv10 device type when compiling a set of logic equations. in addition, many device programmers have two separate selections for the device, typically a gal22lv10 and a gal22lv10-ues (ues = user electronic signature). this allows users to maintain compatibility with existing 22v10 designs, while still having the option to use the gal device's extra feature. the jedec map for the gal22lv10z and gal22lv10zd contains the 64 extra fuses for the electronic signature, for a total of 5892 fuses. however, gal22lv10z and gal22lv10zd devices can still be programmed with a standard 22v10 jedec map (5828 fuses) with any qualified device programmer. security cell a security cell is provided in every gal22lv10z and gal22lv10zd device to prevent unauthorized copying of the array patterns. once programmed, this cell prevents further read access to the functional bits in the device. this cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. the electronic sig- nature is always available to the user, regardless of the state of this control cell. device programming gal devices are programmed using a lattice semiconductor- approved logic programmer, available from a number of manu- facturers (see the the gal development tools section). complete programming of the device takes only a few seconds. erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. output register preload when testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. this is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). to test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. then the machine can be sequenced and the outputs tested for correct next state conditions. gal22lv10z and gal22lv10zd devices include circuitry that allows each registered output to be synchronously set either high or low. thus, any present state condition can be forced for test sequencing. if necessary, approved gal programmers capable of executing test vectors perform output register preload automati- cally. input buffers gal22lv10z and gal22lv10zd devices are designed with ttl level compatible input buffers. these buffers have a characteris- tically high impedance, and present a much lighter load to the driving logic than bipolar ttl devices. input transition detection (itd) the gal22lv10z relies on its internal input transition detection cir- cuitry to put the device into power down mode. if there is no input transition for the specified period of time, the device will go into the power down state. transition detection on any input or i/o will put the device back into the active state. any input pulse widths greater than 5ns at an input transition voltage level of 1.5v will be detected as an input transition. the device will not detect input pulse widths less than 1ns measured at an input transition voltage level of 1.5v as an input transition. dedicated power-down pin the gal22lv10zd uses pin 5 as the dedicated power-down signal to put the device into the standby state. dpp is an active high signal. a logic high driven onto this signal puts the device into the standby state. input pin 5 cannot be used as a logic function in- put on this device. discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications gal22lv10z gal22lv10zd 13 vcc (min.) t pr internal register reset to logic "0" device pin reset to logic "1" t wl t su device pin reset to logic "0" vcc clk internal register q - output active low output register active high output register power-up, some conditions must be met to provide a valid power- up reset of the device. first, the v cc rise must be monotonic. sec- ond, the clock input must be at a static ttl level as shown in the diagram during power up. the registers will reset within a maxi- mum of tpr time. as in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. the clock must also meet the minimum pulse width require- ments. circuitry within the gal22lv10z and gal22lv10zd provides a reset signal to all registers during power-up. all internal registers will have their q outputs set low after a specified time (tpr, 10 s max). as a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. this feature can greatly simplify state machine design by providing a known state on power-up. because of the asynchronous nature of system typical output typical input vcc pin tri-state control feedback (to input buffer) pin feedback data output vcc pin vcc esd protection circuit esd protection circuit vcc pin power-up reset input/output equivalent schematics discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications gal22lv10z gal22lv10zd 14 normalized tpd vs vcc supply voltage (v) normalized tpd 0.8 0.9 1 1.1 1.2 3.00 3.15 3.30 3.45 3.60 pt h->l pt l->h normalized tco vs vcc supply voltage (v) normalized tco 0.8 0.9 1 1.1 1.2 3.00 3.15 3.30 3.45 3.60 rise fall normalized tsu vs vcc supply voltage (v) normalized tsu 0.8 0.9 1 1.1 1.2 3.00 3.15 3.30 3.45 3.60 pt h->l pt l->h normalized tpd vs temp temperature (deg. c) normalized tpd 0.6 0.8 1 1.2 1.4 1.6 -55 -25 0 25 50 75 100 125 pt h->l pt l->h normalized tco vs temp temperature (deg. c) normalized tco 0.6 0.8 1 1.2 1.4 1.6 -55 -25 0 25 50 75 100 125 rise fall normalized tsu vs temp temperature (deg. c) normalized tsu 0.6 0.8 1 1.2 1.4 1.6 -55 -25 0 25 50 75 100 125 pt h->l pt l->h delta tpd vs # of outputs switching number of outputs switching delta tpd (ns) -0.8 -0.6 -0.4 -0.2 0 12345678910 rise fall delta tco vs # of outputs switching number of outputs switching delta tco (ns) -0.8 -0.6 -0.4 -0.2 0 12345678910 rise fall delta tpd vs output loading output loading (pf) delta tpd (ns) -4 -2 0 2 4 6 8 10 12 14 0 50 100 150 200 250 300 rise fall delta tco vs output loading output loading (pf) delta tco (ns) -4 -2 0 2 4 6 8 10 12 14 0 50 100 150 200 250 300 rise fall gal22lv10z/zd: typical ac and dc characteristic diagrams discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
specifications gal22lv10z gal22lv10zd 15 vol vs iol iol (ma) vol (v) 0 0.2 0.4 0.6 0.8 0.00 10.00 20.00 30.00 40.00 voh vs ioh ioh (ma) voh (v) 0 0.5 1 1.5 2 2.5 3 0.00 10.00 20.00 30.00 40.00 voh vs ioh ioh (ma) voh (v) 2.85 2.88 2.91 2.94 2.97 3.00 0.00 1.00 2.00 3.00 4.00 normalized icc vs vcc supply voltage (v) normalized icc 0.8 0.9 1 1.1 1.2 3 3.15 3.3 3.45 3.6 normalized icc vs temp temperature (deg. c) normalized icc 0.8 0.9 1 1.1 1.2 -55 -25 0 25 50 75 100 125 normalized icc vs freq. frequency (mhz) normalized icc 0.6 1.0 1.4 1.8 2.2 0 20406080100 delta icc vs vin (1 input) vin (v) delta icc (ma) 0 1 2 3 4 0 0.5 1 1.5 2 2.5 3 3.5 input clamp (vik) vik (v) iik (ma) 0 40 80 120 160 200 -1.20 -1.00 -0.80 -0.60 -0.40 -0.20 0.00 normalized icc vs freq. (itd) frequency (khz) normalized icc 0 0.2 0.4 0.6 0.8 1 1 10 100 1000 10000 gal22lv10z/zd: typical ac and dc characteristic diagrams discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
notes 16 discontinued product (pcn #02-06). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm

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